In the monolithic integrated circuit technology, it is usually necessary to isolate various active and passive elements from one another in the integrated circuit structure. These devices have been isolated by back biasing, PN junctions, partial dielectric isolation and complete dielectric isolation. The dielectric materials used in dielectric isolation techniques have been silicon dioxide, glass, and so forth. The preferred isolation for these active devices and circuits is some form of dielectric isolation. Dielectric isolation in integrated circuit devices has a substantial advantage over the PN junction isolation because potentially it allows the butting of the circuit elements against the isolation regions and thereby achieves greater density of packing of the active and passive devices on the integrated circuit device.
One form of dielectric isolation involves the formation of grooves or depressions in silicon where the isolation regions are to be formed. During the groove formation, the remainder of the silicon surface is protected by a protective film which is substantially unaffected by the silicon etch used to form the grooves and also to an oxidizing environment. The usual protective layer is a silicon nitride, silicon dioxide, sandwich layer. Following the formation of the grooves by conventional chemical etching, the silicon body is subjected to a conventional oxidation step whereby the silicon in the groove area is oxidized and the silicon dioxide fills up the groove as well as oxidizing further into the silicon to form the isolation region. One of the major problems with this process is what is known as "bird's beak."
The "bird's beak" is a nonplanar silicon dioxide formation at the top periphery of the groove and is caused by the lateral oxidation underneath the silicon nitride layer. Since the oxidation of a specific thickness of silicon requires an almost equivalent amount of free space to expand into, and since the Si.sub.3 N.sub.4 limits the unrestricted expansion, the result is an up-pushing of the silicon nitride at the edge of the groove. The final consequence of this is a general stress in the perimeter region of the groove as well as difficulties in subsequently achieving good butted diffusions against the vertical portion of the silicon dioxide. This non-butting capability defeats a major benefit of the original purpose of the silicon dioxide region. Emitter-butted transistors that do not leak and resistors that do not short are a major problem. This process is described more fully by E. Kooi U.S. Pat. No. 3,970,486, Clevenger U.S. Pat. No. 3,534,234, Peltzer U.S. Pat. No. 3,648,125 and I. Magdo et al, patent application Ser. No. 150,609, filed June 7, 1971.
Another technique for forming dielectric isolation is described in the V. Y. Doo U.S. Pat. No. 3,386,865 and "A Composite Insulator-Junction Isolation" by R. E. Jones and V. Y. Doo, published in Electrochemical Technology, Vol. 5, No. 5-6, May-June 1967, pp. 308-310. This technique involves the formation of a silicon dioxide layer or similar type of layer on the substrate in the region where dielectric isolation is desired. An epitaxial layer is grown upon the substrate in all regions except where the silicon dioxide is located leaving openings over the silicon dioxide. The surface of the epitaxial layer and the sides of the resultant openings are partially thermally oxidized. The openings are partially thermally oxidized. The openings are then filled by vapor deposition of polycrystalline silicon, silicon dioxide or similar materials. This technique has some disadvantages. Selective epitaxy, as required by this technique, is very sensitive to the area relationship between silicon dioxide and silicon regions. For example, two different size silicon regions would tend to fill in at a different rate so that at the end of a process the regions are filled in to a different extent. Also, in mesa-type depositions, crystallographic faceting tends to occur. This results in pyramid-like growth and tends to widen the isolation regions beyond the original lithography capabilities. The slanted silicon/silicon dioxide interface will again cause difficulties in achieving reliable butted diffusions against the silicon dioxide region. Emitter-butted transistors that do not leak and resistors that do not short are a major problem.
The formation of grooves and the filling of such grooves have been described by other publications such as the G. L. Kuhn, U.S. Pat. Nos. 3,892,608 and 3,969,168. In these patents, chemical etching is used to form a V groove, a rounded bottom groove, or a rectangular evacuated space. There is little detail as to how the groove is formed but it is clear that the groove would be limited by the nature of the chemical etching step. The process does not necessarily yield a planar surface and it requires photolithography after the formation of the grooves. D. K. Roberson U.S. Pat. No. 3,956,033 describes a similar chemical etch followed by filling with polycrystalline silicon. Here again, the groove is limited by the chemical etching technique and it is unclear how the overgrowth of the polysilicon is removed. U.S. Patents K. E. Bean et al U.S. Pat. No. 3,725,160 and W. R. Morcom et al U.S. Pat. No. 3,979,237 also show filling of grooves. In these patents, the effect of chemical etching is more clearly brought out where it is shown that monocrystalline silicon are preferentially etched chemically to provide grooves having symmetrical sidewalls sloped at precise angles depending upon the particular face crystal to which the silicon surface is aligned.
U.S. Pat. Nos. 4,104,086 and 4,016,077 both disclose processes for forming deep recessed oxide isolation regions in a silicon substrate wherein grooves are formed in a silicon substrate wherein grooves are formed in the substrate using reactive ion etching, a layer of SiO.sub.2 formed on the surface to fill the grooves, and the SiO.sub.2 layer subsequently removed everywhere on the surface except where the material is disposed in the grooves.
Other methods for forming highly dense and very small, integrated semiconductor devices are described in H.B. Pogge, U.S. Pat. No. 4,256,514; I. T. Ho et al, U.S. Pat. No. 4,209,350; and J. Riseman, U.S. Pat. No. 4,234,362. The one micrometer technology, deep and shallow trench technology and polybase technology described in these patents provide lower collector-isolation capacitance, lower collector-base capacitance, lower base resistance and low diffusion capacitance. However, emitter-butted devices formed by this technology have high leakage and resistors butted against these trenches or mesas cannot be fabricated without adding an extra mask because of what is known as a "side rail" effect. Side rails are thin regions of doped polysilicon on the vertical sides of the mesas that are not removed in the reactive ion etching step which is used to remove the polysilicon. It is to be noted that some of these patents describe mesa sidewalls that are substantially vertical and cannot be more than 5.degree. from the vertical.